1. Field of the Invention
The present invention relates generally to a phase change memory device and, more particularly, to a phase change memory cell array suitable for the implementation of a high-density memory device.
2. Description of the Related Art
With the popularization of portable devices, demands for nonvolatile memory devices are increasing. As for the nonvolatile memory devices, ferroelectric memory, magnetic memory and phase change memory, except for flash memory that is widely used at present, have attracted attention. Especially, the phase change memory can overcome the disadvantages of the flash memory, such as a slow access speed and a limitation in the number of times of use, and solve the problem in which a high voltage is required at the time of operation. Therefore, research has focused on the development of the phase change memory to develop new promising memory devices.
The phase change memory is a memory device using Chalcogenide-based phase change materials mainly including Te or Se of Chalcogene elements belonging to group 16 (VIA) of the periodic table as the material of a resistance element. In particular, Ge—Sb—Te (mainly, Ge2Sb2Te5)-based materials are mainly used as phase change materials. A phase change resistance element exhibits the phase change characteristics in which the phase of a material is changed from a crystalline phase to an amorphous phase and vice versa according to the application conditions of thermal energy depending on the initial state of the material. The two phases have considerable differences in physical characteristics, such as an optical constant and resistivity, and the characteristics can be used in a memory device for performing the recording, removal and reproduction of information.
FIG. 1a is a graph used to explain a digital data storage device that uses the electrical characteristics of the phase change resistance element used in the phase change memory device.
If the phase change resistance element is heated to a melting point and then rapidly cooled by applying a high-voltage amorphizing reset pulse for a short time, as shown in the drawing, a phase change material is amorphised. Additionally, if the phase change resistance element is heated to the temperature between a crystallization temperature Tc and a melting point Tm by applying a low-voltage crystallizing set pulse for a long time, the phase change material is crystallized. The resistivity of the phase change resistance element varies during a phase change, and the resistivity in the amorphous phase is higher than that in the crystalline phase. In the phase change memory device, the state where the phase change resistance element is in a low-resistance crystalline phase is defined as a ‘set’ or ‘ON’ state, and the state where the phase change resistance element is in a high-resistance amorphous phase is defined as a ‘reset’ or ‘OFF’ state. The two states correspond to the logic values ‘0’ and ‘1’ of each memory cell, respectively.
FIG. 1b is a graph showing the resistance variations of the phase change resistance element according to a current pulse normalized to a critical reset current pulse value. In the graph, it can be understood that, when an initial state is a set state, there is no change attributable to the increase of a pulse size and, thereafter, the initial state is transitions to a reset state at or above a critical reset current (which is indicated by ‘□’). In contrast, when an initial state is a reset state, the initial state is first transitions to the crystalline phase according to the increase of the pulse size and, thereafter, transitions to the reset state at or above the critical reset current (which is indicated by ‘▪’). Furthermore, as understood from the graph, the resistivity in the reset state is different from that in the set state 100 or more times, which assures that a sufficient signaling ratio can be secured only by the phase change of the local region of the phase change resistance element.
FIG. 2 is a circuit diagram showing the equivalent circuit of a conventional memory unit cell using the phase change resistance element.
Referring to FIG. 2, a phase change memory cell includes a single access transistor TA, such as a Field Effect Transistor (FET), and a phase change resistance element GST. The lower electrode of the phase change resistance element GST is connected to the source of the transistor TA, and the upper electrode thereof is connected to a plate electrode PL. The drain of the access transistor TA is connected to a bit line BL and the gate thereof is connected to a word line. The construction of the conventional phase change memory unit cell is similar to that of a dynamic random access memory (DRAM) unit cell, except for the substitution of a capacitor with the phase change resistance element.
FIG. 3 is a cross section showing the sectional structure of a conventional phase change memory device formed on a semiconductor substrate using the phase change memory cell of FIG. 2 as the unit thereof.
Referring to FIG. 3, isolation layer 36 for defining the active region of a semiconductor device are formed in the predetermined regions of a semiconductor substrate 30. A pair of word lines 38 functioning as the gates of transistors, respectively, is arranged in parallel to intersect the active region. The word lines 38 define the source regions 42 and drain region 40 of the transistors. That is, the active region between the pair of word lines 38 corresponds to the common drain region 40 of the transistors, and the two regions outside the word lines 38 correspond to the source regions 42 of the transistors. As shown in the drawing, a first interlayer-dielectric 48 is placed on the semiconductor substrate 30 and the tops of the transistors, and the common drain region 40 of the transistors is electrically connected to the bit line 44 through a bit line contact that passes through the first interlayer-dielectric 48. A second interlayer-dielectric 50 is placed on the first interlayer insulation film 48 including the bit line 44, and phase change resistance elements 65 each including a lower electrode 52, a phase change resistance film 62a and an upper electrode 64a are formed on the second interlayer-dielectric 50. The phase change resistance elements 65 are electrically connected to the source regions 42 of the transistors through contacts 46, respectively, which pass through the first and second interlayer-dielectrics 48 and 50. Even though not shown in the drawing, a planar interlayer-dielectric is placed on the phase change resistance elements 65, and a plate electrode is placed on the planar interlayer insulation film.
As described above, in the conventional phase change memory device, the common drain region on the semiconductor substrate is electrically connected to the bit line through the bit line contact. In such a structure, a sufficient space for a contact forming process should be secured on the common drain, which unavoidably increases an area occupied by the unit cell. Accordingly, the conventional phase change memory device adopts a cell structure unsuitable for the implementation of a high-density phase change memory device.